1. Field of the Invention
The present invention relates to a reference voltage generating circuit, and more particularly to a MOS-type reference voltage generating circuit.
2. Description of the Background Art
FIG. 1 illustrates a conventional reference voltage generating circuit using a voltage difference Vgs between a gate and a source of an NMOS transistor.
First and second PMOS transistors P11, P12 constitute a current mirror and first and second NMOS transistors N11, N12 are respectively connected between each drain of the first and second PMOS transistors P11, P12 and a ground. A back-bias voltage Vbb is applied to each substrate of the first and second NMOS transistors N11, N12 for the purpose of effectively diminishing a threshold voltage change, and gates of the first and second NMOS transistors N11, N12 are commonly connected to an output node A.
The operation of the thusly constructed reference voltage generating circuit will be described hereinafter with reference to the accompanying drawings.
In FIG. 1, each of the PMOS transistors P11, P12 has the identical length and width. On the other hand, the NMOS transistors N11, N12 have the same length but a width of the first NMOS transistor N11 is greater than that of the second NMOS transistor N12 (W.sub.n11 &gt;W.sub.n12). Here, it is assumed that the ratio of the width of the first NMOS transistor N11 and that of the second NMOS transistor N12 is K (K=W.sub.n11 /W.sub.n12), and currents towards the NMOS transistors N11, N12 are indicated as I.sub.n11, I.sub.n12, respectively.
On such an assumption, an operation current applied to the output node A from the NMOS transistors N11, N12 may be represented by a following equation (1). ##EQU1##
Here, Vgs(N12) denotes a voltage difference between the gate and source of the NMOS transistor N12 and Vgs(N11) is a voltage difference between the gate and source of the NMOS transistor N11.
If the NMOS transistors N11, N12 operate in a saturation region, each of the currents I.sub.n11, I.sub.n12, which are applied to the first and the second NMOS transistors N11, N12, respectively, may be expressed as follows. ##EQU2##
Here, Vtn denotes a threshold voltage of the NMOS transistors N11, N12, V.sub.B denotes a voltage of a node B (V.sub.B =I.sub.N11.times.R1), and each of .beta..sub.1, .beta..sub.2 which are the process parameters represents a transconductance. In addition, it is noted that ##EQU3##
wherein U.sub.N is electronic mobility of each of the NMOS transistors, .epsilon. is a dielectric constant, and t.sub.ox is a gate oxide thickness.
Thus, by virtue of the current mirror operation of the PMOS transistors P11, P12, when equalizing the values of the currents I.sub.n11, I.sub.n12, being applied to the NMOS transistors N11, N12, respectively, an equation (4) can be obtained from the equations (2) and (3). ##EQU4##
Accordingly, the operation current (I.sub.OP =I.sub.N11 =I.sub.N12), and a reference voltage Vref can be represented with each of equations as follows. ##EQU5##
Thus, according to the equation (6), since the reference voltage Vref is determined by the threshold voltage Vtn, resistance R1, the process parameter .beta..sub.2, and a constant K, the reference voltage Vref may be generated irrespective of any change of a power supply voltage Vcc.
In addition, an effect of a temperature change on the reference voltage Vref may appear dependently upon a temperature change of each of the above parameters. Namely, the threshold voltage Vtn generally has -1 mV/.degree. C. of a temperature dependency, and the resistance R of which a gate is formed of a doped polysilicon has +0.01/.degree. C. thereof. Also, the electronic mobility U.sub.N varies by ##EQU6##
each time in accordance with temperature, and thus the process parameter .beta..sub.2 also shows ##EQU7##
of a temperature dependency.
Accordingly, when ##EQU8##
is to have +1 mV/.degree. C. of the temperature dependency, the reference voltage Vref can be generated, regardless of any temperature change.
In the conventional reference voltage generating circuit, however, the threshold voltage Vtn of the NMOS transistors N11, N12 may vary in accordance with the back-bias voltage Vbb which is applied to the corresponding substrates of the first and second NMOS transistors N11, N12.
That is to say, a bulk of each of the NMOS transistors N11, N12 is connected to a p-type substrate and the p-type substrate is biased at a negative back-bias voltage Vbb which is generated inside a chip device. Accordingly, the back-bias voltage Vbb generates a voltage difference Vsb between the source and the bulk of each of the NMOS transistors N11, N12, and thus has an effect on the threshold voltage Vtn as a following equation (7). EQU Vtn=Vtn0+.gamma.Vsb (7)
In the equation (7), Vtn0 is the value of the threshold voltage Vtn when Vsb=0, .gamma. is a body effect factor which has a value of the range between 0.4 to 1.2 according to doping condition, and Vsb is the voltage difference between the source and the bulk of the NMOS transistor.
FIG. 2 is a graph which illustrates a change of the threshold voltage Vtn in accordance with which the back-bias voltage Vbb varies, and shows that as an absolute value of the back-bias voltage Vbb increases, the threshold voltage Vtn thus correspondingly increases.
FIG. 3 is a graph illustrating a simulation result which shows a change of the reference voltage Vref with respect to the back-bias voltage Vbb. The reference voltage Vref is not considerably affected by the change of the power supply voltage Vcc when the back-bias voltage Vbb is uniformly maintained; however, when the back-bias voltage Vbb changes, the voltage Vref accordingly has a dependency of +178 mV/V. Moreover, since the back-bias voltage Vbb is generally equivalent to -1/2 of the power supply voltage Vcc, the absolute value of the back-bias voltage Vbb also increases as the power supply voltage Vcc increases. As a result, when the absolute value of the back-bias voltage Vbb increases, the threshold voltage Vtn increases in accordance therewith and thus the reference voltage Vref consequently increases, which leads to the problem.